The present invention relates to a prescaler and a PLL circuit, and more specifically, to a PLL circuit that matches an output signal frequency with a predetermined frequency.
Phase-locked loop (PLL) circuits are used in mobile communication devices, such as cellular telephones. To improve the performance of the mobile communication device, a PLL circuit must quickly shift an output signal frequency to the desired frequency. Accordingly, it is required that the lockup time of the PLL circuit be decreased.
FIG. 1 is a schematic block diagram showing a prior art PLL circuit. The PLL circuit includes an oscillator 1, which generates a reference clock signal CK having an inherent frequency corresponding to the oscillation of a crystal oscillating element. The clock signal CK is provided to a reference frequency divider 2. The reference frequency divider 2 includes a counter circuit, divides the frequency of the reference clock signal CK in accordance with a division ratio determined by a shift register 3 to generate a reference signal fr, and provides the reference signal fr to a phase comparator 4.
The phase comparator 4 provides a charge pump 6 with pulse signals "PHgr"R, "PHgr"P corresponding to the frequency difference or phase difference between the reference signal fr and a comparison signal fp.
The charge pump 6 provides an output signal SCP corresponding to the pulse signals "PHgr"R, "PHgr"P to a low-pass filter (LPF) 7.
The output signal SCP has DC components, which include pulse components. The DC components shift in accordance with the frequency fluctuation of the pulse signals "PHgr"R, "PHgr"P, and the pulse components shift in accordance with the phase difference of the pulse signals "PHgr"R, "PHgr"P.
The LPF 7 smoothes and eliminates high frequency components from the output signal SCP of the charge pump 6 to generate an output signal SLPF, which is provided to a voltage-controlled oscillator (VCO) 8.
The VCO 8 generates an oscillation output signal fvco, which has a frequency corresponding to the voltage value of the output signal SLPF of the LPF 7, and provides the oscillation output signal fvco to an external circuit and a comparison frequency divider 5.
The comparison frequency divider 5 is a pulse-swallow type, and includes a prescaler 9, a main counter 10, a swallow counter 11, and a control circuit 12.
The prescaler 9 divides the frequency of the input signal (the oscillation output signal fvco of the VCO 8) by M or by (M+1) to generate a prescaler divisional signal Pout. Then, the prescaler 9 provides the prescaler divisional signal Pout to the main counter 10 and the swallow counter 11.
The swallow counter 11 divides the prescaler divisional signal Pout by A and provides a swallow counter divisional signal to the control circuit 12. In accordance with the swallow counter divisional signal, the control circuit 12 provides the prescaler 9 with, for example, a high module control signal MD. In accordance with the module control signal MD, the prescaler 9 divides the frequency of the oscillation output signal fvco by M to output the prescaler divisional signal Pout.
While the swallow counter 11 is counting an A number of pulses, the control circuit 12 provides the prescaler 9 with, for example, a low module control signal MD. In accordance with the module control signal MD, the prescaler 9 divides the frequency of the oscillation output signal fvco by (M+1) to output the prescaler divisional signal Pout.
The shift register 3 determines a division ratio N of the main counter 10. The main counter 10 divides the frequency of the prescaler divisional signal Pout by N to generate the comparison signal fp and provides the comparison signal fp to the phase comparator 4. The divisional signal (comparison signal) fp of the main counter 10 is also provided to the control circuit 12. The control circuit 12 provides the swallow counter 11 with an activation signal each time the main counter 10 divides the frequency of the prescaler divisional signal Pout by N.
Accordingly, every time the main counter 10 divides the prescaler divisional signal Pout by N in the above PLL circuit, the swallow counter 11 is activated and the prescaler divisional signal Pout is counted.
FIG. 2 is a schematic circuit diagram showing the prior art prescaler 9. The oscillation output signal fvco of the VCO 8 is input to synchronous flip-flop circuits FF1, FF2, FF3, which form a frequency division shifting circuit C, as input signals CK, XCK through a buffer circuit 13. It is preferred that each of the flip-flop circuits FF1-FF3 be a D flip-flop (delay flip-flop) circuit.
The flip-flop circuit FF1 provides output signals QH, XQH as data XD, D, respectively, to the flip-flop circuit FF2. The flip-flop circuit FF2 provides its QH output signal to a first input terminal of an OR circuit 14a and its XQH output signal to a first input terminal of an OR circuit 14b. 
The OR circuit 14a provides an output signal as data to the flip-flop circuit FF1. The OR circuit 14b provides an output signal as data to the flip-flop circuit FF3. The flip-flop circuit FF3 provides its output signal XQH to a second input terminal of the OR circuit 14a. 
Two T-type flip-flop circuits TFF1, TFF2, which form an asynchronous extender circuit E, are provided. The flip-flop circuit FF1 provides its XQ output to the flip-flop circuit TFF1 as its CK input signal.
The flip-flop circuit TFF1 provides its output signal Q as the input signal CK to the flip-flop circuit TFF2. The flip-flop circuit TFF2 provides its output signal Q to a buffer circuit 15. The buffer circuit 15 outputs the prescaler divisional signal Pout.
A bias circuit 16 provides the input signal XCK, which has a constant voltage, to the flip-flop circuits TFF1, TFF2.
The output signals QH of the flip-flop circuits TFF1, TFF2 are provided to first and second input terminals of an OR circuit 14c. A third input terminal of the OR circuit 14c is provided with the module control signal MD. The OR circuit 14c provides its output signal OR to a second input terminal of the OR circuit 14b. 
The flip-flop circuits TFF1, TFF2 are each configured as shown in FIG. 3. The flip-flop circuits TFF1, TFF2 each invert the output signal Q and complementary output signals QH, XQH whenever the clock signal CK goes high. Accordingly, the flip-flop circuits TFF1, TFF2 divide the output signal XQ of the flip-flop circuit FF1 by four.
FIG. 4 is a timing chart showing the operation of the prescaler 9. When the prescaler 9 is provided with the oscillation output signal fvco of the VCO 8, the operation of the flip-flop circuits FF1, FF2 causes the flip-flop circuit FF1 to divide the oscillation output signal fvco by four and generate the output signal XQ.
The output signal Q of the flip-flop circuit TFF1 is generated by dividing the output signal XQ of the flip-flop circuit FF1 by two, that is, by dividing the oscillation output signal fvco by eight. Further, the output signal Q of the flip-flop circuit TFF2 is generated by dividing the oscillation output signal fvco by sixteen.
When the module control signal MD is low, the output signal OR of the OR circuit 14c is determined by the QH output signals of the flip-flop circuits TFF1, TFF2.
Until the prescaler 9 counts twelve pulses of the oscillation output signal fvco from a count initiation point SP, at least one of the output signals QH of the flip-flop circuits TFF1, TFF2 is high. Thus, the output signal OR of the OR circuit 14c is high. In this state, the output signal XQH of the flip-flop circuit FF3 is fixed at a low level.
When the prescaler 9 counts twelve pulses of the oscillation output signal fvco, the output signals QH of the flip-flop circuits TFF1, TFF2 both go low. Thus, the output signal OR of the OR circuit 14c goes low. In this state, the flip-flop circuit FF3 is activated. Thus, the operation of the flip-flop circuits FF1-FF3 causes the flip-flop circuit FF1 to generate the output signal XQ by dividing the input signal fvco by five.
Accordingly, when the module control signal MD is low, the prescaler 9 divides the oscillation signal fvco by (M+1), or by seventeen.
When the module control signal MD is high, the output signal OR of the OR circuit 14c is fixed to a high level. Thus, the flip-flop circuit FF3 is de-activated and the output signal XQH is fixed at a low level. Accordingly, if the module control signal MD is high, the prescaler 9 divides the oscillation signal fvco by M, or by sixteen.
In the PLL circuit, when the dividing operation of the swallow counter 11 is initiated, the module control signal MD goes low, and the prescaler 9 divides the oscillation signal fvco by (M+1).
In the prescaler 9, however, a time delay Td occurs from when the division by (M+1) is initiated at the count initiation point SP to when the module control signal MD falls. The time delay Td is determined by adding the operation delay times of the extender circuit E of the prescaler 9, the swallow counter 11, and the control circuit 12. The ratio of the operation delay time of the flip flop circuits TFF1, TFF2 in the delay time Td is large.
The delay time Td is substantially constant regardless of the frequency of the oscillation output signal fvco provided by the prescaler 9. Thus, a margin time Tm decreases as the frequency of the oscillation output signal fvco increases.
When the frequency of the oscillation output signal fvco increases and the delay time Td becomes longer than one cycle of the output signal Q of the flip-flop circuit TFF2, the prescaler 9 cannot perform the (M+1) division. As a result, the lock-up operation based on the frequency obtained by the (M+1) division cannot be performed.
It is an object of the present invention to provide a prescaler and a PLL circuit incorporating the prescaler that prevents abnormal functioning when switching the division ratio.
To achieve the above object, the present invention provides a prescaler including a frequency division shifting circuit for shifting a frequency division ratio in response to a frequency division ratio shifting signal and dividing an input signal in accordance with the shifted frequency division ratio to generate a first divisional signal. An extender circuit is connected to the frequency division shifting circuit to divide the frequency of the first divisional signal with a predetermined frequency division ratio and generate a second divisional signal. The extender circuit includes a synchronous counter.
A further aspect of the present invention provides a prescaler including a frequency division shifting circuit for shifting a frequency division ratio in response to a frequency division ratio shifting signal and dividing an input signal in accordance with the shifted frequency division ratio to generate a first divisional signal. An extender circuit is connected to the frequency division shifting circuit to divide the frequency of the first divisional signal with a predetermined frequency division ratio and generate a second divisional signal. The extender circuit includes an asynchronous counter connected to a synchronous counter.
Another aspect of the present invention provides a PLL circuit including a reference frequency divider for dividing the frequency of a reference clock signal to generate a reference signal. A phase comparator is connected to the reference frequency divider to compare a phase of the reference signal with a phase of a comparison signal to generate a phase comparison signal. A charge pump is connected to the phase comparator to convert the phase comparison signal to a voltage signal. A low-pass filter is connected to the charge pump to smooth the voltage signal and generate a smooth signal. A voltage-controlled oscillator is connected to the low-pass filter to generate an oscillation output signal having a frequency corresponding to the voltage of the smooth signal. A comparison frequency divider is connected to the voltage-controlled oscillator and the phase comparator to divide the frequency of the oscillation output signal and generate the comparison signal. The comparison frequency divider includes a prescaler for dividing the frequency of the oscillation output signal with a frequency division ratio corresponding to a module control signal to generate a prescaler divisional signal. A main counter is connected to the prescaler to divide the frequency of the prescaler divisional signal and generate the comparison signal. A swallow counter is connected to the prescaler to divide the frequency of the prescaler divisional signal and generate a swallow counter divisional signal. A control circuit is connected to the swallow counter and the main counter to generate the module control signal in accordance with the comparison signal and the swallow counter divisional signal. The prescaler includes a frequency division shifting circuit for shifting the frequency division ratio in response to a frequency division ratio shifting signal and dividing an input signal in accordance with the shifted frequency division ratio to generate a first divisional signal. An extender circuit is connected to the frequency division shifting circuit to divide the frequency of the first divisional signal with a predetermined frequency division ratio and generate a second divisional signal. The extender circuit includes a synchronous counter.
A further aspect of the present invention provides a PLL circuit including a reference frequency divider for dividing the frequency of a reference clock signal to generate a reference signal. A phase comparator is connected to the reference frequency divider to compare a phase of the reference signal with a phase of a comparison signal and generate a phase comparison signal. A charge pump is connected to the phase comparator to convert the phase comparison signal to a voltage signal. A low-pass filter is connected to the charge pump to smooth the voltage signal and generate a smooth signal. A voltage-controlled oscillator is connected to the low-pass filter to generate an oscillation output signal having a frequency corresponding to the voltage of the smooth signal. A comparison frequency divider is connected to the voltage-controlled oscillator and the phase comparator to divide the frequency of the oscillation output signal and generate the comparison signal. The comparison frequency divider includes a prescaler for dividing the frequency of the oscillation output signal with a frequency division ratio corresponding to a module control signal to generate a prescaler divisional signal. A main counter is connected to the prescaler to divide the frequency of the prescaler divisional signal and generate the comparison signal. A swallow counter is connected to the prescaler to divide the frequency of the prescaler divisional signal and generate a swallow counter divisional signal. A control circuit is connected to the swallow counter and the main counter to generate the module control signal in accordance with the comparison signal and the swallow counter divisional signal. The prescaler includes a frequency division shifting circuit for shifting the frequency division ratio in response to a frequency division ratio shifting signal and dividing an input signal in accordance with the shifted frequency division ratio to generate a first divisional signal. An extender circuit is connected to the frequency division shifting circuit to divide the frequency of the first divisional signal with a predetermined frequency division ratio and generate a second divisional signal. The extender circuit includes an asynchronous counter connected to a synchronous counter.
Other aspects and advantages of the present invention will become apparent from the following description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention.